`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/31 11:55:54
// Design Name: 
// Module Name: decode
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module decode(
    clk,inst,nop,opcode,opcode_id,rs1,rs2,rd,funct3,funct7,imm_1,imm_2,imm_3,imm_4
    );

    input clk,nop;
    input [31:0] inst;
    output [6:0] opcode;
    output [4:0] rs1,rs2;
    output [2:0] funct3;
    output [6:0] funct7;
    output reg [6:0] opcode_id;
    output reg [4:0] rd;
    output reg [4:0] imm_1;
    output reg [11:0] imm_2;
    output reg [6:0] imm_3;
    output reg [19:0] imm_4;

    assign opcode = inst[6:0];
    assign funct3 = inst[14:12];
    assign funct7 = inst[31:25];
    assign rs1 = inst[19:15];
    assign rs2 = inst[24:20];
    
    always @(posedge clk) begin
        if(nop) begin
            rd <= 5'bx;
            imm_1 <= 5'bx;
            imm_2 <= 12'bx;
            imm_3 <= 7'bx;
            imm_4 <= 20'bx;
            opcode_id <= 7'bx;
        end
        else begin
            rd <= inst[11:7];
            imm_1 <= inst[11:7];
            imm_2 <= inst[31:20];
            imm_3 <= inst[31:25];
            imm_4 <= inst[31:12];
            opcode_id <=inst[6:0];
        end
    end
endmodule
